Rajesh Rengarajan
27Patents
11h-index
50Co-inventors
74Inventor score
Filing activity: Dec 30, 1997 → Jan 12, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6501131B1 | Transistors having independently adjustable parameters | Electricity | 56 | Expired |
| US6635526B1 | Structure and method for dual work function logic devices in vertical DRAM process | Electricity | 46 | Expired |
| US5940717A | Recessed shallow trench isolation structure nitride liner and method for making same | Emerging Cross-Sectional Technologies | 44 | Expired |
| US6869866B1 | Silicide proximity structures for CMOS device performance improvements | Electricity | 24 | Expired |
| US6323103A | Method for fabricating transistors | Electricity | 21 | Expired |
| US6329704A | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Electricity | 21 | Expired |
| US6194278A | Device performance by employing an improved method for forming halo implants | Electricity | 20 | Expired |
| US6960818B1 | Recessed shallow trench isolation structure nitride liner and method for making same | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6074903A | Method for forming electrical isolation for semiconductor devices | Electricity | 12 | Expired |
| US6521493B1 | Semiconductor device with STI sidewall implant | Electricity | 11 | Expired |
| US6740920B2 | Vertical MOSFET with horizontally graded channel doping | Electricity | 11 | Expired |
| US6127215A | Deep pivot mask for enhanced buried-channel PFET performance and reliability | Electricity | 10 | Expired |
| US6197632A | Method for dual sidewall oxidation in high density, high performance DRAMS | Electricity | 7 | Expired |
| US6960523B2 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Electricity | 7 | Expired |
| US6426247B1 | Low bitline capacitance structure and method of making same | Electricity | 6 | Expired |
| US6724053B1 | PMOSFET device with localized nitrogen sidewall implantation | Electricity | 6 | Expired |
| US9355887B2 | Dual trench isolation for CMOS with hybrid orientations | Electricity | 6 | Active |
| US6387782B2 | Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | Electricity | 3 | Expired |
| US8097516B2 | Dual trench isolation for CMOS with hybrid orientations | Electricity | 2 | Active |
| US7572689B2 | Method and structure for reducing induced mechanical stresses | Electricity | 1 | Active |
| US7314790B2 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Electricity | 1 | Active |
| US7161169B2 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Electricity | 1 | Expired |
| US7883948B2 | Method and structure for reducing induced mechanical stresses | Electricity | 0 | Active |
| US6867087B2 | Formation of dual work function gate electrode | Electricity | 0 | Expired |
| US7462525B2 | Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.