Integrated circuit structure with improved LDMOS design
US6870218B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A semiconductor integrated circuit including an LDMOS device structure includes a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.