Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor
US6870771B2 · kind B2 · utility
4Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Jul 24, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Sep 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.