Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
US6871267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2001 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Jul 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system includes a system bus communicating between processors, and a bus arbiter. Responsive to a cache line invalidation command, a processor cache conditionally casts back the cache line to a transition cache. Based on the system response to the invalidation command, the transition cache either discards the cast back or writes it to main memory. The processor also converts an exclusive read command requiring a reservation to non-exclusive if the reservation has been lost before placing the command on the system bus. Furthermore, the transition cache may shift memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command involving the same real address is snooped. Responsive to a cache line request, the cache copies that cache line to the transition cache and updates cache line state. The transition cache holds the cache line pending system response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.