Method for mapping logic design memory into physical memory device of a programmable logic device
US6871328B1 · kind B1 · utility
30Cited by
4References
77Claims
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Key dates
| Filing date | Nov 14, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.