Inventor · Thornhill, MB, CA

Ketan Padalia

22Patents
8h-index
23Co-inventors
71Inventor score

Filing activity: Nov 14, 2002 → Apr 27, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US6871328B1 Method for mapping logic design memory into physical memory device of a programmable logic device Physics 30 Expired
US9569574B1 Method and apparatus for performing fast incremental physical design optimization Physics 22 Active
US8281274B1 Method and apparatus for performing efficient incremental compilation Physics 17 Active
US7681165B2 Apparatus and methods for congestion estimation and optimization for computer-aided design software Physics 16 Active
US7558812B1 Structures for LUT-based arithmetic in PLDs Electricity 13 Expired
US7268584B1 Adder circuitry for a programmable logic device Physics 10 Expired
US8504970B1 Method and apparatus for performing automated timing closure analysis for systems implemented on target devices Physics 8 Active
US7493585B1 Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks Physics 8 Active
US7370291B2 Method for mapping logic design memory into physical memory devices of a programmable logic device Physics 7 Expired
US8539418B1 Method and apparatus for performing efficient incremental compilation Physics 7 Active
US9594859B1 Apparatus and associated methods for parallelizing clustering and placement Physics 6 Active
US7415682B2 Automatic adjustment of optimization effort in configuring programmable devices Physics 3 Expired
US7707532B1 Techniques for grouping circuit elements into logic blocks Physics 3 Active
US7441208B1 Methods for designing integrated circuits Physics 2 Active
US8856713B1 Method and apparatus for performing efficient incremental compilation Physics 1 Active
US8499273B1 Systems and methods for optimizing placement and routing Physics 1 Active
US7275228B1 Techniques for grouping circuit elements into logic blocks Physics 1 Expired
US11093672B2 Method and apparatus for performing fast incremental physical design optimization Physics 1 Active
US8788550B1 Structures for LUT-based arithmetic in PLDs Electricity 1 Active
US10073941B1 Method and apparatus for performing efficient incremental compilation Physics 0 Active
US10635772B1 Method and apparatus for performing fast incremental physical design optimization Physics 0 Active
US9658830B1 Structures for LUT-based arithmetic in PLDs Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.