Selective formation of metal gate for dual gate oxide application
US6872627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Dec 1, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.