Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof
US6873004B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.