ESD protection for semiconductor products
US6873017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | May 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
Device 60 in FIG. 3 has junctions 86 each with a lateral portion 90 and a second portion 92 extending upward toward the surface 12 from the lateral portion 90. The lateral portions 90, as illustrated in FIG. 3, are more or less formed along a plane parallel with the surface 12. The upwardly extending portions 92 include characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regions 80 and 82 each having relatively high net dopant concentrations of different conductivity types, each lateral junction portion 90 includes a relatively large sub region 96 which extends more deeply into the layer 10. When compared to other portions of the junctions 86, the subregions 96 are characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.