Methods of making microelectronic packages including electrically and/or thermally conductive element
US6873039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jun 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a plurality of microelectronic packages including electrically and/or thermally conductive elements. The method includes providing a support structure having a plurality of protrusions and depressions extending outwardly from the support. A conductive element is then mated to the support structure in a male-to-female relationship. The depressions formed in the support structure and conductive element are used to house a microelectronic element such as a semiconductor chip. A substrate is provided so as to cover substantially each depression located in the conductive element. Leads interconnect contacts to the chip to terminals on the substrate. A curable encapsulant material may be deposited into the depression so as to protect and support the leads and the microelectronic element. Additionally, the curable encapsulant material forms part of the exterior of a single resulting chip package once the assembly is diced and cut into individual packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.