Method and apparatus for controlling signal distribution in an electronic circuit
US6873187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1506
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay. The integer nonlinear program comprises a system of monotone difference constraints on finite integer ranges, and is solvable utilizing a modified Bellman-Ford algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.