Patent · US Expired

Method and circuit arrangement for picture-in-picture fade-in

US6873370B1 · kind B1 · utility

1Cited by

5References

3Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Maik Brett · Schweinhub, DE
Marko Hahn · Neubiberg, DE

Key dates

Filing date	Apr 3, 2000
Grant date	Mar 29, 2005
Priority date	—
Expiry date	Apr 3, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH04N5/45
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A method and a circuit arrangement for picture-in-picture insertion are described, in which, in order to prevent a write operation from being overtaken by a read operation and also to avoid the associated picture disturbances, a field is stored under an address which precedes a previous field by a number of N lines. A read address is then shifted to the same line of the older field in the event of a minimum distance to a write address being undershot.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.