Shared data buffer in FeRAM utilizing word line direction segmentation
US6873536B2 · kind B2 · utility
55Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Apr 19, 2002 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a data buffer, and a sense amplifier between several segments of an array of FeRAM memory cells associated with a plurality of plate lines and/or word lines of the array. Various combinations of segmented bit lines, segmented plate lines and/or segmented word lines facilitate sharing the memory circuits of the device between the array segments or multiple arrays of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.