High capacity MRAM memory array architecture
US6873547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Mar 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic memory is disclosed. The magnetic memory includes a first magnetic tunneling junction and a reference magnetic tunneling junction. The first magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and a first insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The reference magnetic tunneling junction includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second insulating layer between the third ferromagnetic layer and the fourth ferromagnetic layer. The magnetic memory also includes means for comparing a first output of the first magnetic tunneling junction with a reference output of the reference magnetic tunneling junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.