Cache-flushing engine for distributed shared memory multi-processor computer systems
US6874065B1 · kind B1 · utility
23Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a “flush” command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a “flush request” is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.