Context processing by substantially simultaneously selecting address and instruction of different contexts
US6874080B2 · kind B2 · utility
3Cited by
8References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, a processor unit executing the instructions in a pipelined fashion, a plurality of context registers for storing instructions and instruction addresses for contexts to be executed and fetch logic for selecting an address from one of the context registers and for selecting an instruction from a second of the context registers for execution substantially simultaneously for each cycle of execution of processor unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.