Method for reactive ion etch processing of a dual damascene structure
US6875688B1 · kind B1 · utility
4Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 2004 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | May 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for implementing dual damascene processing includes forming a first hardmask layer over an interlevel dielectric layer, and forming a second hardmask layer over the first hardmask layer. A trench pattern is opened within a third hardmask layer formed over the second hardmask. A first etch process is implemented so as to define a via pattern completely through the second hardmask layer and partially through the first hardmask layer, and a second etch process is implemented to transfer the trench pattern and the via pattern into the interlevel dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.