Inventor · Heverlee, BE

Kaushik A. Kumar

53Patents
10h-index
97Co-inventors
77Inventor score

Filing activity: Dec 11, 2002 → Apr 19, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US6975032B2 Copper recess process with application to selective capping and electroless plating Electricity 51 Expired
US7057287B2 Dual damascene integration of ultra low dielectric constant porous materials Electricity 20 Expired
US7084479B2 Line level air gaps Electricity 16 Expired
US7470616B1 Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention Electricity 16 Active
US8367544B2 Self-aligned patterned etch stop layers for semiconductor devices Electricity 15 Active
US7629264B2 Structure and method for hybrid tungsten copper metal contact Electricity 14 Active
US7122462B2 Back end interconnect with a shaped interface Electricity 14 Expired
US7064064B2 Copper recess process with application to selective capping and electroless plating Electricity 13 Expired
US7241696B2 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Electricity 12 Expired
US7052621B2 Bilayered metal hardmasks for use in Dual Damascene etch schemes Emerging Cross-Sectional Technologies 12 Expired
US7049209B1 De-fluorination of wafer surface and related structure Electricity 9 Expired
US7241681B2 Bilayered metal hardmasks for use in dual damascene etch schemes Emerging Cross-Sectional Technologies 9 Expired
US8551877B2 Sidewall and chamfer protection during hard mask removal for interconnect patterning Electricity 9 Active
US7224021B2 MOSFET with high angle sidewall gate and contacts for reduced miller capacitance Electricity 8 Expired
US8592327B2 Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage Electricity 8 Active
US7253098B2 Maintaining uniform CMP hard mask thickness Electricity 7 Expired
US7358182B2 Method of forming an interconnect structure Electricity 7 Active
US7659160B2 Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same Electricity 7 Active
US7648871B2 Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same Electricity 5 Active
US7091612B2 Dual damascene structure and method Electricity 5 Expired
US8809194B2 Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch Emerging Cross-Sectional Technologies 5 Active
US6875688B1 Method for reactive ion etch processing of a dual damascene structure Electricity 4 Expired
US7737561B2 Dual damascene integration of ultra low dielectric constant porous materials Electricity 4 Active
US7888252B2 Self-aligned contact Electricity 4 Active
US8945408B2 Etch process for reducing directed self assembly pattern defectivity Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.