High voltage N-LDMOS transistors having shallow trench isolation region

US6876035B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wagdi W. Abadeer · Jericho, US
• Jeffrey S. Brown · Jeffersonville, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Jed H. Rankin · South Burlington, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: May 6, 2003
• Grant date: Apr 5, 2005
• Expiry date: May 6, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.