Shift register chain for trimming generators for an integrated semiconductor apparatus
US6876586B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor apparatus includes at least one fuse box device that includes fuses for storing trimming data, a fuse box trimming output, and a timer emitting a clock signal. The apparatus also includes a parallel/serial converter that is connected to the fuses and to the timer. The parallel/serial converter is configured to read, in parallel, the trimming data from the fuses and to emit, in serial, the trimming data from the fuse block trimming output based on the clock signal. The apparatus also includes generators. Each generator generates a generator signal and includes a trimming unit that has a trimming signal input. The trimming unit is configured to trim the generator signal of the generator based on the trimming data received. The generator also includes a trimming signal output and memory flip-flops that connect the trimming input signal to the trimming output signal. Each of the memory flip-flops connects each trimming unit to the fuse block trimming output to form a shift register chain for serial transmission of the trimming data from the fuse block device to the generators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.