2T2C signal margin test mode using a defined charge exchange between BL and/BL
US6876590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.