Decoder circuit with function of plural series bit line selection
US6876596B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Nov 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line decoding circuit for accessing an array of two-bit memory cells. Two adjacent memory cells can be accessed by applying appropriate voltages to the terminals of the cells. A bit line decoder selects plural bit lines in the memory array and provides paths to apply or receive the voltages to or from the selected bit lines. In one embodiment, shared control gates of pass transistors which function as the bit line selection in a bit line deocder provides reduction in the number of control signals. Functions of applying a voltage for neighbor effect reduction and of providing a path for a reference voltage are also implemented in further embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.