Method and apparatus for memory with embedded processor
US6877046B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Nov 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one form, a computer system includes a system processor operable to process data. The system includes a number of memory array chips coupled to the system processor by a system bus. Such a memory array chip includes random access memory partitioned into rows, each row having a number of memory words. The random access memory has an internal buffer and the buffer is operable to hold a plurality of the memory words. Such a memory array chip includes an embedded processor and an internal bus coupling the embedded processor to the internal buffer. The internal bus is capable of concurrently transferring the plurality of memory words of the internal buffer for processing by the embedded processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.