Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving
US6877087B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Apr 21, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.