Method of forming thick metal silicide layer on gate electrode
US6878598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0213
Abstract
Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.