Triple-well charge pump stage with no threshold voltage back-bias effect
US6878981B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/078
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A charge pump stage includes a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal. A second n-channel transistor has a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate coupled to the output terminal. A third n-channel transistor has a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a p-well. A fourth n-channel transistor has a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the p-well. The first, second, third and fourth transistors are fabricated in the p-well, which is surrounded by an n-well. A first capacitor is coupled to the output terminal, and a second capacitor is coupled to the gate of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.