MOS power transistor
US6878996B2 · kind B2 · utility
12Cited by
4References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 29, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
Abstract
An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a manner spatially isolated from the source electrode zone. The particular integration structure of the MOS power transistor avoids a parasitic drain-bulk diode, a parasitic body diode and a substrate diode and thereby achieves an area-saving protection against over-currents in the event of reverse voltage polarity between drain and source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.