Multi-processor computer system with transactional memory
US6880045B2 · kind B2 · utility
37Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Sep 2, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.