Sharing a second tier cache memory in a multi-processor
US6880049B2 · kind B2 · utility
121Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2002 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/822
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.