Method for improving capacitor noise and mismatch constraints in a semiconductor device
US6880134B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | May 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method (50) is provided for improving switched capacitor performance by lowering a mismatch constraint to be equal to, or nearly equal to, a noise constraint. The mismatch constraint is lowered by increasing a finger spacing of a fringe capacitor design (10) while maintaining the same surface area covered by the fringe capacitor design (10). In another embodiment, a noise constraint is lowered by decreasing finger spacing. Lowering the noise constraint by decreasing finger spacing reduces the area of a fringe capacitor used in, for example, an analog-to-digital converter. Both embodiments may improve performance of the analog-to-digital converter by lowering power consumption, increasing speed, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.