Semiconductor device that include silicide layers
US6882018B2 · kind B2 · utility
42Cited by
13References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Nov 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.