Quad flat no-lead chip carrier
US6882057B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Sep 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar through holes distributed around a chip-bonding region. The conductive columns are set up within the columnar through holes. The dielectric walls are set up between the sidewall of the conductive columns and the inner surface of the columnar through holes. The chip is electrically connected to the conductive columns via conductive wires. The bottom end of the conductive columns serves as input/output contacts for connecting with external contacts. The chip carrier is able to increase overall density of the input/output contacts and improve the electrical performance of the chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.