Memory repeater
US6882082B2 · kind B2 · utility
81Cited by
10References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2001 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4256
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and associated apparatus are provided for improving the performance of a high speed data bus, such as a memory bus, using selectively activated receiver and driver pairs. Each receiver and driver pair may be selectively activated to permit data communication on a segment of the high speed data bus coupled to the activated receiver and driver pair. Each receiver and driver pair may also be deactivated, thereby disconnecting at least a respective segment of the high speed data bus, so that communicating system components may be connected in a substantially stubless environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.