Parallel programming of multiple-bit-per-cell memory cells on a continuous word line
US6882567B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operations reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing. During or at the end of write operations, remedial programming sequences can adjust the threshold voltages of memory cells that program slowly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.