Synchronous controlled, self-timed local SRAM block
US6882591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. One embodiment relates to a memory device comprising a muxing device and at least one cluster device coupled to the muxing device. Another embodiment comprises a method of performing at least one of a read and write operation in a memory device. The method comprises activating at least one cluster device in the memory device and firing at least one sense amp in the at least one cluster device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.