PC and ATE integrated chip test equipment
US6883128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.