Site-specific methodology for localization and analyzing junction defects in mosfet devices
US6884641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Sep 18, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/902
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.