Method for dishing reduction and feature passivation in polishing processes
US6884724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2001 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Aug 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.