Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
US6885044B2 · kind B2 · utility
40Cited by
43References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/92
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.