Double-gate FinFET device and fabricating method thereof
US6885055B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Feb 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
Abstract
The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction.The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.