Techniques for processing out-of-order requests in a processor-based system
US6886048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2001 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Jan 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1626
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.