Hierarchical test circuit structure for chips with multiple circuit blocks
US6886121B2 · kind B2 · utility
41Cited by
22References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2001 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | May 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks are a socket access port (SAP) controller. Test operation is transferred downward and upwards within said hierarchical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.