Bulent Dervisoglu
19Patents
12h-index
5Co-inventors
71Inventor score
Filing activity: Aug 10, 1990 → Feb 14, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5257223A | Flip-flop circuit with controllable copying between slave and scan latches | Electricity | 106 | Expired |
| US6594802B1 | Method and apparatus for providing optimized access to circuits for debug, programming, and test | Physics | 89 | Expired |
| US6631504B2 | Hierarchical test circuit structure for chips with multiple circuit blocks | Physics | 80 | Expired |
| US6687865B1 | On-chip service processor for test and debug of integrated circuits | Physics | 69 | Expired |
| US6886121B2 | Hierarchical test circuit structure for chips with multiple circuit blocks | Physics | 41 | Expired |
| US7197681B2 | Accelerated scan circuitry and method for reducing scan test data volume and execution time | Physics | 25 | Expired |
| US7890899B2 | Variable clocked scan test improvements | Physics | 22 | Active |
| US7181705B2 | Hierarchical test circuit structure for chips with multiple circuit blocks | Physics | 21 | Expired |
| US7353470B2 | Variable clocked scan test improvements | Physics | 20 | Active |
| US7188286B2 | Accelerated scan circuitry and method for reducing scan test data volume and execution time | Physics | 19 | Expired |
| US5068881A | Scannable register with delay test capability | Physics | 18 | Expired |
| US7200784B2 | Accelerated scan circuitry and method for reducing scan test data volume and execution time | Physics | 18 | Expired |
| US6964001B2 | On-chip service processor | Physics | 8 | Expired |
| US7752515B2 | Accelerated scan circuitry and method for reducing scan test data volume and execution time | Physics | 6 | Active |
| US7836371B2 | On-chip service processor | Physics | 4 | Active |
| US7080301B2 | On-chip service processor | Physics | 4 | Expired |
| US8239716B2 | On-chip service processor | Physics | 2 | Active |
| US8996938B2 | On-chip service processor | Physics | 1 | Active |
| US6816996B2 | Hierarchical test circuit structure for chips with multiple circuit blocks | General | 0 | Revoked |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.