Wafer thickness control during backside grind
US6887126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Aug 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.