Multi-layered resist structure and manufacturing method of semiconductor device
US6887649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/146
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided steps of forming a lower resist layer on a patterning objective layer, forming an organic intermediate layer made of organic material, that contains no Si—O bond in its structure, on the lower resist layer, forming an upper resist layer made of alicyclic resin on the organic intermediate layer, forming a pattern by exposing/developing the upper resist layer, transferring the pattern of the upper resist layer onto the organic intermediate layer by etching the organic intermediate layer while using the upper resist layer as a mask, transferring a pattern of the organic intermediate layer onto the lower resist layer by etching the lower resist layer while using the organic intermediate layer as a mask, and etching the patterning objective layer while using the lower resist layer as a mask. Accordingly, a semiconductor device manufacturing method containing patterning steps employing a multi-layered resist structure, that is capable of suppressing deformation of the pattern of the upper resist layer formed of alicyclic compound, can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.