High performance, low cost microelectronic circuit package with interposer
US6888240B2 · kind B2 · utility
130Cited by
47References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Apr 30, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low cost technique for packaging microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuit using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core assembly before lamination of the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.