Semiconductor wafer testing system
US6888365B2 · kind B2 · utility
6Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.