FPGA peripheral routing with symmetric edge termination at FPGA boundaries
US6888374B2 · kind B2 · utility
4Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.