Low-voltage non-volatile semiconductor memory device
US6888756B2 · kind B2 · utility
6Cited by
9References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Apr 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is a non-volatile semiconductor memory device including a bias circuit that generates a bias voltage for controlling an NMOS transistor connected to both a bit line and a page buffer circuit. The bias circuit generates a first voltage, which is greater than a power source voltage, as the bias signal in a precharge period of a read operation. The bias circuit also generates a second voltage, which is less than the power source voltage, as the bias signal in a sensing period of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.