Multimode system for calibrating a data strobe delay for a memory read operation
US6889334B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Aug 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.